One type of prior non-volatile semiconductor memory is flash electrically erasable programmable read-only memory ("flash memory"). Flash memory can be programmed by a user, and once programmed, the flash memory retains its data until erased. After erasure, the flash memory may be programmed with new data.
Flash memories differ from conventional electrically erasable programmable read only memory ("EEPROMs") with respect to erasure. Conventional EEPROMs typically use a select transistor for individual byte erase control. Flash memories, on the other hand, typically achieve much higher density with single transistor cells. Flash memories typically achieve faster erase speeds by erasing all memory cells in a memory array simultaneously.
According to flash terminology, a logical "one" means that few if any electrons are stored on a floating gate associated with a bit cell. A logical "zero" means that many electrons are stored on the floating gate associated with the bit cell. Erasure of a flash memory cell causes it to store a logical one. A flash memory cell can only be written from a logical zero to a logical one by erasure of the entire array. Memory cells can, however, be individually overwritten from a logical one to a logical zero, given that this entails simply adding electrons to a floating gate.
One prior flash memory is the 28F008 CMOS flash memory sold by Intel Corporation of Santa Clara, Calif. The 28F008 is an eight megabit flash memory, which incorporates a prior write state machine. The prior write state machine automatically programs and erases the array upon receipt of a two stage command from the command port. In response to an erase command, the prior write state machine performs two major tasks: array preconditioning and array erasure. Preconditioning the nonvolatile memory array brings memory cell threshold voltages to a minimum level of approximately 5.3 volts, representative of a logic zero, and prolongs the longevity of the nonvolatile memory array by preventing cell threshold voltages from dropping to levels during erasure that could result in memory cell leakage. Preconditioning is performed much like programming. That is, preconditioning is performed by applying approximately 12 volts to memory cell gates, 5-7 volts to memory cell drains, and grounding memory cell sources.
FIG. 1 illustrates in flow diagram form a prior method of preconditioning a nonvolatile memory array, which was implemented by the prior write state machine of the 28F008. According to the prior method a group of memory cells, typically a byte, is selected for preconditioning and is operated upon until the selected group of memory cells verifies as preconditioned. In other words, the selected group of memory cells is always verified immediately after application of a precondition pulse. If the selected group of memory cells do not verify as being preconditioned, then another precondition pulse is immediately applied to that group of memory cells. When the selected group of memory cells verifies, another group of memory cells is selected for preconditioning. This process requires frequently pausing while voltage levels applied to the nonvolatile memory array slew (i.e., ramp or change) between high precondition levels and lower verify levels. Given that a block of memory may include 64 Kbytes of data, much erase time is attributable to voltage level slewing during preconditioning. In the prior 28F008 flash memory, preconditioning alone can consume up to approximately 40% of the approximately one second block erase time.